Senior Hardware Design Engineer – ASIC & High-Speed Systems
We are recruiting on behalf of a leading global technology organisation for an experienced Senior Hardware Design Engineer to develop complex, high-speed hardware for advanced communication systems.
Key Responsibilities
Develop hardware architectures and translate system requirements into detailed designs.
Design Evaluation Boards (EVBs) for ASIC validation, characterisation and system integration.
Design high-speed clocking, power delivery and Power Distribution Networks (PDNs).
Perform Power Integrity (PI) and Signal Integrity (SI) analysis.
Develop schematics and define PCB stack-up, HDI and multilayer PCB requirements.
Work closely with PCB layout teams and review schematic, placement and routing.
Support board bring-up, hardware debugging, validation and characterisation.
Develop test plans and technical documentation.
Support DFM/DFT reviews and production ramp-up.
Key Requirements
Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
8+ years’ experience in hardware design and development of complex electronic systems.
Proven experience taking hardware from architecture and schematic design through to board bring-up and ASIC validation.
Strong experience with high-speed SerDes, ideally at 26.4Gbps+.
Experience with power supply design, power sequencing, high-current power delivery and PDN optimisation.
Strong understanding of SI, PI and IR drop analysis.
Experience with high-layer-count PCB, HDI and high-speed design.
Proficiency with Cadence OrCAD Capture, Allegro or equivalent.
Experience with MCU/microprocessor hardware and interfaces including DDR, Ethernet, SPI, I²C, UART and SDIO.
Experience with high-frequency RF design, ideally 10GHz+, is highly desirable.
Hands-on experience with oscilloscopes, spectrum/signal analysers, VNAs and power analysers.
Strong troubleshooting and root-cause analysis skills.
Experience with mixed-signal design, manufacturing, reliability testing or ASIC development is advantageous.